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this p roduct conform s to specifications per the terms of the ramtron ramtron international corporation standard warranty. the product has completed ramtrons internal 1850 ramtron drive, colorado springs, co 80921 qualification testing and has reached production status . (800) 545 - fram, (7 19) 481 - 7000 rev. 3.0 www.ramtron.com jan. 2012 page 1 of 12 fm 24cl04b 4kb serial 3v f - ram memory features 4k bit ferroelectric nonvolatile ram ? organized as 512 x 8 bits ? high endurance 10 1 4 read/writes ? 38 year data retention ? nodelay? writes ? advanced high - reliability ferroelectric process fast two - wire serial i nterface ? up to 1 mhz maximum bus frequency ? direct hardware replacement for eeprom ? supports legacy timing for 100 khz & 400 khz low power operation ? 2.7v to 3.65v operation ? 100 ? a active current (100 khz) ? 3 ? a (typ.) standby current industry standard configuration ? industrial temperature - 40 ? c to +85 ? c ? 8 - pin green /rohs soic ( - g) description the fm 24cl04b is a 4 - kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or fram is nonvolatile and per forms reads and writes like a ram. it provide s reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. t he fm 24cl04b performs write operatio ns at bus speed. no write delays are incurred. data is written to the memory array in the cycle after it has been successfully transferred to the device. the next bus cycle may commence immediately without the need for data polling . the fm24c l 04b is capabl e of supporting 10 1 4 read/write cycles, or a million times more write cycles than eeprom. these capabilities make the fm 24cl04b ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection where the nu mber of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the combination of features allows more frequent data writing with less overhead for the system. the fm 24cl04b provides substa ntial benefits to users of serial eeprom, yet these benefits are available in a hardware drop - in replacement. the fm 24cl04b is available in an industry standard 8 - pin soic package and uses a familiar two - wire protocol. the specifications are guaranteed ove r an ind ustrial temperature range of - 40c to +85c. pin configuration pin names function a1 - a2 device select address 1 and 2 sda serial data/address scl serial clock wp write protect vss ground vdd supply voltage ordering information f m24cl04b - g green/rohs 8 green/rohs 8 nc a1 a2 vss vdd wp scl sda 1 2 3 4 8 7 6 5
FM24CL04B rev. 3.0 jan. 2012 page 2 of 12 figure 1. block diagram pin description pin name i/o pin description a1 - a2 input address 1 - 2: the address pins set the device sele ct address. the device address value in the 2 - wire slave address must match the setting of these two pins. these pins are internally pulled down. sda i/o serial data/address: this is a bi - directional pin used to shift serial data and addresses for the tw o - wire interface. it employs an open - drain output and is intended to be wire - ord with other devices on the two - wire bus. the input buffer incorporates a schmitt trigger for noise immunity and the output driver includes slope control for falling edges. a p ull - up resistor is required. scl input serial clock: the serial clock input for the two - wire interface. data is clocked out of the device on the scl falling edge, and clocked in on the scl rising edge. the scl input also incorporates a schmitt trigger inp ut for improved noise immunity. wp input write protect: when wp is high , the entire array is write - protected. when wp is low, all addresses may be written. this pin is internally pulled down. nc - no connect vdd supply supply voltage vss supply groun d address latch 64 x 64 fram array data latch 8 sda counter serial to parallel converter control logic scl wp a 1 a 2
FM24CL04B rev. 3.0 jan. 2012 page 3 of 12 overview the fm 24cl04b is a serial fram memory. the memory array is logically organized as 512 x 8 and is accessed using an industry standard two - wire interface. functional operation of the fram is similar to serial eeproms. the major difference betwe en the fm 24cl04b and a serial eeprom with the same pinout relates to its superior write performance. memory architecture when accessing the fm 24cl04b , the user addresses 512 locations each with 8 data bits. these data bits are shifted serially. the 512 ad dresses are accessed using the two - wire protocol, which includes a slave address (to distinguish other devices), a page address, and a word address. the word address consists of 8 - bits that specify one of 256 addresses. the page address is 1 - bit and so the re are 2 pages of 256 locations. the complete address of 9 - bits specifies each byte address uniquely. most functions of the fm 24cl04b either are controlled by the two - wire interface or are handled automatically by on - board circuitry. the memory is read o r written at the speed of the two - wire bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. that is, by the time a new bus transaction can be shifted into the part, a write operation will be c omplete. this is explained in more detail in the interface section below. users can expect several obvious system benefits from the fm 24cl04b due to its fast write cycle and high endurance as compared with eeprom. however there are less obvious benefits as well. for example in a high noise environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast an eeprom requiring milliseconds to write is vulnerable to noise during much of the cycle . note that the fm 24cl04b contains no power management circuits other than a simple internal power - on reset. it is the users responsibility to ensure that v dd is within data sheet tolerances to prevent incorrect operation. two - wire interface the fm 24c l04b employs a bi - directional two - wire bus protocol using few pins and little board space. figure 2 illustrates a typical system configuration using the fm 24cl04b in a microcontroller - based system. the industry standard two - wire bus is familiar to many use rs but is described in this section. by convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. the device that is controlling the bus is the master. the master is responsible for generating the clock signal for all operations. any device on the bus that is being controlled is a slave. the fm 24cl04b is always a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions: start, stop, data bit, and acknowledge. figure 3 illustrates the signal conditions that specify the four states. detailed timing diagrams are shown in the electrical specifications. figure 2. typical system configuration microcontroller sda scl fm 24 cl 04 b a 1 a 2 sda scl fm 24 cl 04 b a 1 a 2 vdd rmin = 1 . 1 kohm rmax = tr / cbus
FM24CL04B rev. 3.0 jan. 2012 page 4 of 12 figure 3. data transfer protocol stop condition a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations must end with a stop condition. if an operation is pe nding when a stop is asserted, the operation will be aborted. the master must have control of sda (not a memory read) in order to assert a stop condition. start condition a start condition is indicated when the bus master drives sda from high to low while the scl signal is high. all read and write transactions begin with a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will ready the fm 24cl04b for a new op eration. if during operation the power supply drops below the specified v dd minimum, the system should issue a start condition prior to performing another operation. data/address transfer all data transfers (including addresses) take place while the scl signal is high. except under the two conditions described above, the sda signal should not change while scl is high. acknowledge the acknowledge takes place after the 8 th data bit has been transferred in any transaction. during this state the transmitter should release the sda bus to allow the receiver to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the condition is a no - acknowledge and the operation is aborted. the receiver could fail to acknowledge for two distinct reasons. first, if a byte transfer fails, the no - acknowledge ends the current operation so that the device can be addressed again. this allows the last byte to be recovered in the event of a communication error. s econd and most common, the receiver does not acknowledge the data to deliberately end an operation. for example, during a read operation, the fm 24cl04b will continue to place data onto the bus as long as the receiver sends acknowledges (and clocks). when a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. if the receiver acknowledges the last byte, this will cause the fm 24cl04b to attempt to drive the bus on the next clock while the master is sending a n ew command such as a stop command. slave address the first byte that the fm 24cl04b expects after a start condition is the slave address. as shown in figure 4, the slave address contains the device type, the device select, the page of memory to be accessed , and a bit that specifies if the transaction is a read or a write. bits 7 - 4 are the device type and should be set to 1010b for the fm 24cl04b . the device type allows other types of functions to reside on the 2 - wire bus within an identical address range. bits 3 - 2 are the device address. if bit 3 matches the a2 pin and bit 2 matches the a1 pin the device will be selected. bit 1 is the page select. it specifies the 256 - byte block of memory that is targeted for the current operation. bit 0 is the read/write b it. a 0 indicates a write operation. word address after the fm 24cl04b (as receiver) acknowledges the slave id, the master will place the word address on the bus for a write operation. the word address is the lower 8 - bits of the address to be combined wit h the 1 - bit page select to specify exactly the byte to be written. the complete 9 - bit address is latched internally.
FM24CL04B rev. 3.0 jan. 2012 page 5 of 12 figure 4. slave address no word address occurs for a read operation. reads always use the lower 8 - bits that are held i nternally in the address latch and the 9 th address bit is part of the slave address. reads always begin at the address following the previous access. a random read address can be loaded by doing a write operation as explained below. after transmission of each data byte, just prior to the acknowledge, the fm 24cl04b increments the internal address latch. this allows the next sequential byte to be accessed with no additional addressing. after the last address (1ffh) is reached, the address latch will roll ov er to 000h. there is no limit to the number of bytes that can be accessed with a single read or write operation. data transfer after all address information has been transmitted, data transfer between the bus master and the fm 24cl04b can begin. for a read operation the fm 24cl04b will place 8 data bits on the bus then wait for an acknowledge. if the acknowledge occurs, the next sequential byte will be transferred. if the acknowledge is not sent, the read operation is concluded. for a write operation, the fm 24cl04b will accept 8 data bits from the master then send an acknowledge. all data transfer occurs msb (most significant bit) first. memory operation the fm 24cl04b is designed to operate in a manner very similar to other 2 - wire interface memory products. the major differences result from the higher performance write capability of fram technology. these improvements result in some differences between the fm 24cl04b and a similar configuration eeprom during writes. the complete operation for both writes and reads is explained below. write operation all writes begin with a slave address then a word address. the bus master indicates a write operation by setting the lsb of the slave address to a 0. after addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. any number of sequential bytes may be written. if the end of the address range is reached internally, the address counter will wrap from 1ffh to 000h. unlike other nonvolatile memory technologies , there is no write delay with fram. the entire memory cycle occurs in less time than a single bus clock. therefore any operation including read or write can occur immediately following a write. acknowledge polling, a technique used with eeproms to determi ne if a write is complete is unnecessary and will always return a done condition. an actual memory array write occurs after the 8 th data bit is transferred. it will be complete before the acknowledge is sent. therefore if the user desires to abort a writ e without altering the memory contents, this should be done using a start or stop condition prior to the 8 th data bit. the fm 24cl04b needs no page buffering. the memory array can be write protected using the wp pin. pulling wp high will disabl e writes to the entire array. the fm 24cl04b will not acknowledge data bytes that are written when write protect is asserted. in addition, the address counter will not increment if writes are attempted. pulling wp low (v ss ) will deactivate this feature. f igure 5 below illustrates both a single - and multiple - byte write.
FM24CL04B rev. 3.0 jan. 2012 page 6 of 12 figure 5. byte write figure 6. multiple byte write read operation there are two basic types of read operations. they are curr ent address read and selective address read. in a current address read, the fm 24cl04b uses the internal address latch to supply the lower 8 address bits. in a selective read, the user performs a procedure to set these lower address bits to a specific valu e. current address & sequential read the fm 24cl04b uses an internal latch to supply the lower 8 address bits for a read operation. a current address read uses the existing value in the address latch as a starting place for the read operation. this is the address immediately following that of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to 1. this indicates that a read operation is requested. the page select bit in the slave address speci fies the block of memory that is used for the read operation. after the acknowledge, the fm 24cl04b will begin shifting out data from the current address. the current address is the bit from the slave address combined with the 8 bits that were in the intern al address latch. beginning with the current address, the bus master can read any number of bytes. thus a sequential read is simply a current address read with multiple byte transfers. after each byte the internal address counter will be incremented. eac h time the bus master acknowledges a byte, this indicates that the fm 24cl04b should read out the next sequential byte. there are four ways to properly terminate a read operation. failing to properly terminate the read will most likely create a bus contenti on as the fm 24cl04b attempts to read out additional data onto the bus. the four valid methods are as follows. 1. the bus master issues a no - acknowledge in the 9 th clock cycle and a stop in the 10 th clock cycle. this is illustrated in the diagrams below. thi s is the preferred method. 2. the bus master issues a no - acknowledge in the 9 th clock cycle and a start in the 10 th . 3. the bus master issues a stop in the 9 th clock cycle. bus contention may result. 4. the bus master issues a start in the 9 th clock cycle. bus c ontention may result. if the internal address reaches 1ffh it will wrap around to 000h on the next read cycle. figures 7 and 8 show the proper operation for current address reads. selective (random) read a simple technique allows a user to select a random address location as the starting point for a read operation. this involves using the first two bytes of a write operation to set the internal address byte followed by subsequent read operations. to perform a selective read, the bus master sends out the slave address with the lsb set to 0. this specifies a write operation. according to the write protocol, the bus master then sends the word address byte that is loaded into the internal address latch. after the fm 24cl04b acknowledges the word address, the b us master issues a start condition. this simultaneously aborts the write operation and allows the read command to be issued with the slave address lsb set to a 1. the operation is now a current address read. see figure 9. s a slave address 0 word address a data byte a p by master by fm 24 cl 04 b start address & data stop acknowledge s a slave address 0 word address a data byte a p by master by fm 24 cl 04 b start address & data stop acknowledge data byte a
FM24CL04B rev. 3.0 jan. 2012 page 7 of 12 fi gure 7. current address read figure 8. sequential read figure 9. selective (random) read s a s l a v e a d d r e s s 1 d a t a b y t e 1 p b y m a s t e r b y f m 2 4 c l 0 4 s t a r t a d d r e s s s t o p a c k n o w l e d g e n o a c k n o w l e d g e d a t a s a s l a v e a d d r e s s 1 d a t a b y t e 1 p b y m a s t e r b y f m 2 4 c l 0 4 s t a r t a d d r e s s s t o p a c k n o w l e d g e n o a c k n o w l e d g e d a t a d a t a b y t e a a c k n o w l e d g e s a s l a v e a d d r e s s 1 d a t a b y t e 1 p b y m a s t e r b y f m 2 4 c l 0 4 s t a r t a d d r e s s s t o p n o a c k n o w l e d g e d a t a d a t a b y t e a a c k n o w l e d g e s a s l a v e a d d r e s s 0 w o r d a d d r e s s a s t a r t a d d r e s s a c k n o w l e d g e
FM24CL04B rev. 3.0 jan. 2012 page 8 of 12 electrical specifications absolute maximum ratings symbol description ratings v dd power supply volt age with respect to v ss - 1.0v to +5.0v v in voltage on any signal pin with respect to v ss - 1.0v to +5.0v and v in < v dd +1.0v * t stg storage t emperature - 55 ? c to + 125 ? c t lead lead t emperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 3.5kv 1.25kv 250v package moisture sensitivity level msl - 1 * exception: the v in < v dd +1.0v restriction does n ot apply to the scl and sda inputs. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those l isted in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. dc operating conditions (t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 3.65v unless otherwi se specified) symbol parameter min typ max units notes v dd main power supply 2.7 3.3 3.65 v i dd vdd supply current @ scl = 100 khz @ scl = 400 khz @ scl = 1 mhz 100 1 7 0 300 ? a ? a ? a 1 i sb standby current 3 6 ? a 2 i li input leakage current 1 ? a 3 i lo output leakage current 1 ? a 3 v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage - 0.3 0.3 v dd v v ol output low voltage @ i ol = 3.0 ma 0.4 v r in input resistance (wp, a2, a1) for v in = v il (max) for v in = v ih (mi n) 4 0 1 k ? m ? 5 v hys input hysteresis 0.05 v dd v 4 notes 1. scl toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v 2. scl = sda = v dd . all inputs v ss or v dd . stop command issued. 3. v in or v out = v ss to v dd . does not apply to wp, a1, a2 pins . 4. this parameter is periodically sampled and not 100% tested. 5. the input pull - down circuit is strong (40k ? ) when the input voltage is below v il and much weaker (1m ? ) when the input voltage is above v ih .
FM24CL04B rev. 3.0 jan. 2012 page 9 of 12 ac parameters (t a = - 40 ? c to + 85 ? c, v dd = 2.7v t o 3.65v, c l = 100 pf unless otherwise specified) symbol parameter min max min max min max units notes f scl scl clock frequency 0 100 0 400 0 1000 khz t low clock low period 4.7 1.3 0.6 ? s t high clock high period 4.0 0.6 0.4 ? s t aa scl low to sda data out valid 3 0.9 0.55 ? s t buf bus free before new transmission 4.7 1.3 0.5 ? s t hd:sta start condition hold time 4.0 0.6 0.25 ? s t su:sta start condition setup for repeated start 4.7 0.6 0.25 ? s t hd:dat data in hold 0 0 0 ns t su:dat data in setup 250 100 100 ns t r input rise time 1000 300 300 ns 1 t f input fall time 300 300 100 ns 1 t su:sto stop condition setup 4.0 0.6 0.25 ? s t dh data output hold (from scl @ vil) 0 0 0 ns t sp noise suppression time co nstant on scl, sda 50 50 50 ns notes : all scl specifications as well as start and stop conditions apply to both read and write operations. 1 this parameter is periodically sampled and not 100% tested. capacitance ( t a = 25 ? c, f=1.0 mhz, v dd = 3v) s ymbol parameter max units notes c i/o input/ output c apacitance (sda) 8 pf 1 c in input c apacitance 6 pf 1 notes 1 this parameter is periodically sampled and not 100% tested. power cycle timing power cycle timing ( t a = - 40 ? c to +85 ? c , v dd = 2.7v to 3.65v unless otherwise specified ) symbol parameter min max units notes t pu power up (v dd min) to first access (start condition) 10 - ms t pd last access (stop condition) to power down (v dd min) 0 - ? s t vr v dd rise time 30 - ? s/v 1 t vf v dd fall time 3 0 - ? s/v 1 notes 1. sl ope measured at any point on v dd waveform . v d d m i n . v d d s d a , s c l t v r t p d t p u t v f
FM24CL04B rev. 3.0 jan. 2012 page 10 of 12 ac test conditions equivalent ac load circuit input pulse levels 0.1 v dd to 0.9 v dd input rise and fall times 10 ns input and output timing levels 0.5 v dd diagra m notes all start and stop timing parameters apply to both read and write cycles. clock specifications are identical for read and write cycles. write timing parameters apply to slave address, word address, and write data bits. functional relationships are illustrated in the relevant data sheet sections. these diagrams illustrate the timing parameters only. read bus timing write bus timing data retention symbol parameter min max units notes t dr @ +85oc 10 - years @ +80oc 19 - years @ +75oc 38 - years t s u : s d a s t a r t t r ` t f s t o p s t a r t t b u f t h i g h 1 / f s c l t l o w t s p t s p a c k n o w l e d g e t h d : d a t t s u : d a t t a a t d h s c l s d a t s u : s t o s t a r t s t o p s t a r t a c k n o w l e d g e t a a t h d : d a t t h d : s t a t s u : d a t s c l s d a 3 . 6 v output 1100 ? 100 pf
FM24CL04B rev. 3.0 jan. 2012 page 11 of 12 mechanical drawing 8 - pin soic (jedec standard ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in m illimeters . soic package marking scheme legend: xx xx xx= part number, p= package type (g=soic) r=rev code, lllllll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm 24cl04b , green soic package, year 2010, work week 4 9 fm 24c l 04b g a 00002g1 ric1049 xxxx xxxp rll llll l ricyyww p i n 1 3 . 9 0 0 . 1 0 6 . 0 0 0 . 2 0 4 . 9 0 0 . 1 0 0 . 1 0 0 . 2 5 1 . 3 5 1 . 7 5 0 . 3 3 0 . 5 1 1 . 2 7 0 . 1 0 m m 0 . 2 5 0 . 5 0 4 5 0 . 4 0 1 . 2 7 0 . 1 9 0 . 2 5 0 - 8 r e c o m m e n d e d p c b f o o t p r i n t 7 . 7 0 0 . 6 5 1 . 2 7 2 . 0 0 3 . 7 0
FM24CL04B rev. 3.0 jan. 2012 page 12 of 12 revision history revision date summary 1.0 11/10/2010 initial release 1.1 12/20 /2010 changed v ih (max) spec to v dd +0.3v. 1.2 1/31/2011 added esd ratings. 1.3 2/15/2011 changed t pu and t vf spec limit s. 3.0 1/6/2 012 changed to production status. changed t vf spec.

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